1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a designing method of the same, and more particularly to a semiconductor integrated circuit having macro cells and a designing method of the same.
2. Description of the Related Art
In recent years, attention has been paid to a system LSI with a plurality of macro cells on a semiconductor chip, having functions of a central processing unit (CPU), memory devices (ROM, RAM), buffer, peripheral devices that perform various kinds of signal processing, etc.
Since the system LSI comprises the plurality of macro cells, the circuit scale is so large that the direct circuit design for a transistor level cannot be achieved in actuality. For this reason, the system LSI is generally designed in such a manner that a system design, function design, specific logic design and circuit design are sequentially carried out stepwise.
In the system design, each of CPU, ROM, RAM, buffer, the plurality of peripheral devices is provided as one function block, and the operation and structure of the entire system are decided to obtain a desired function. In the function design, the relationship among the respective function blocks and the internal operations of the respective function blocks are decided based on the specification decided by the system design. In the specific logic design, the layout of macro cells for configuring the respective blocks whose internal operations are decided by the function design is performed on the semiconductor chip, and these macro cells are mutually wired (layout wiring) so as to generate a simulation model for a semiconductor integrated circuit. In the circuit design, an electric circuit for a transistor level and the characteristics of devices are decided to satisfy the circuit specification, which is based on the logic design having the function design and the specific logic design.
Here, the macro cells are composed of basic logic devices such as an inverter, a NAND gate, a NOR gate, etc., and basic logic circuits such as a latch, a counter, a memory, etc. formed by combining a plurality of basic logic devices. The macro cells are registered to a memory (library) of a CAD (Computer Aided Design) and the like where the respective functions are described using a programming language such as a hardware description language (HDL), C language (trade name), etc. Data of the simulation model for a semiconductor integrated circuit generated as mentioned above is complied with data of macro cells stored in the memory, thereafter a simulation for an operation is carried out to verify whether or not a desired function is obtained.
FIG. 17 is a top view showing a macro cell of the memory (hereinafter referred to as memory macro) that forms a cell base IC designed by the design method (logic design) of the conventional semiconductor integrated circuit and the peripheral portion thereof. The memory macro has a multi-layer wiring structure. In this example, the explanation is given on the assumption that a three-layer wiring is used.
At an outer edge of a core section 1, the memory macro has a plurality of signal input/output terminals 2, power lead-in ground terminals 3a11, 3a12, 3b11 and 3b12, and power lead-in power terminals 3a21, 3a22, 3b21 and 3b22.
The power lead-in ground terminals 3a11 and 3a12, and the power lead-in power terminals 3a21 and 3a22 are formed by the wiring of second layer, and the power lead-in ground terminals 3b11 and 3b12, and the power lead-in power terminals 3b21 and 3b22 are formed by the wiring of the third layer.
A portion enclosed with a broken line provided at an outside of the core section 1 indicates a region where the memory macro is present, and is called a macro outer frame 4. In an interior of the core section 1, a ground terminal 5a1, a power terminal 5b1, a ground terminal 5a2 and a power terminal 5b2 are formed with a predetermined interval in a vertical direction of the figure. The ground terminals 5a1 and 5a2 and the power terminals 5b1 and 5b2 are formed by the wiring of the fourth layer, and connected to wiring to be connected to the ground and wiring to be connected to the power among wiring of the third layer, respectively.
Orbital power rings 6 and 7 are formed double at the outside of the macro outer frame 4 to surround the macro outer frame 4. The orbital power ring 6 includes horizontal ground wiring 6a1 and 6a2 and vertical ground lines 6b1 and 6b2. The horizontal ground wiring 6a1 and 6a2 are formed by the wiring of the third layer, and the vertical ground lines 6b1 and 6b2 are formed by the wiring of the second layer.
The orbital power ring 7 formed in the vicinity of the outer periphery of the orbital power ring 6 includes horizontal ground wiring 7a1 and 7a2 and vertical power lines 7b1 and 7b2. The horizontal power wiring 7a1 and 7a2 are formed by the wiring of the third layer, and the vertical power lines 7b1 and 7b2 are formed by the wiring of the second layer.
The power lead-in ground terminals 3a11 and 3a21 are connected to power lead-in ground lines 8a11 and 8a21, which are formed by the wiring of the second layer, respectively. Similarly, the power lead-in ground terminals 3a12 and 3a22, are connected to power lead-in ground lines 8a12 and 8a22, which are formed by the wiring of the second layer, respectively.
The power lead-in ground terminals 3b11 and 3b21, are connected to power lead-in ground lines 8b11 and 8b21, which are formed by the wiring of the third layer, respectively. The power lead-in ground terminals 3b12 and 3b22, are connected to power lead-in ground lines 8b12 and 8b22, which are formed by the wiring of the third layer, respectively.
The power lead-in ground lines 8a11 and 8a12 are connected to the horizontal ground wiring 6a1 and 6a2 through via holes, respectively, and the power lead-in ground lines 8a21 and 8a22 are connected to the horizontal power wiring 7a1 and 7a2 through via holes, respectively.
The power lead-in ground lines 8b11 and 8b12 are connected to the vertical ground lines 6b1 and 6b2 through via holes, respectively, and the power lead-in ground lines 8b21 and 8b22 are connected to the vertical power lines 7b1 and 7b2 through via holes, respectively.
The horizontal power ground lines 6a1 and the horizontal power wring 7a1 are connected to a vertical ground bus 9a and a horizontal power bus 9b, which are formed by the wring of the fourth layer, through via holes, respectively.
As illustrated in FIG. 18, the vertical power bus 9a is connected to the horizontal ground wiring 6a2, which constitutes the orbital power ring 6 formed to enclose the macro outer frame 4, through a via hole. Similarly, the vertical power bus 9b is connected to the horizontal power wiring 7a2, which constitutes the orbital power ring 7 formed to enclose the macro outer frame 4, through a via hole.
The vertical ground line 6b2 is connected to a horizontal ground bus 10a formed in the first layer through a via hole, and the vertical power line 7b2 is connected to a horizontal power bus 10b formed in the first layer through a via hole. The horizontal ground bus 10a is connected to the vertical ground line 6b1, which constitutes the orbital power ring 6 formed to enclose the macro outer frame 4, through a via hole. The horizontal power bus 10b is connected to the vertical power line 6b1, which constitutes the orbital power ring 7 formed to enclose the macro outer frame 4, through a via hole.
In this way, the orbital power rings 6 and 7 are formed to enclose the macro outer frame 4 for each macro cell, and a current is supplied to the macro cell from the corresponding orbital ring.
Moreover, if a horizontal power bus 11a and a horizontal ground bus 11b on a semiconductor substrate (semiconductor chip) formed by the wiring of fifth layer pass on the memory macro, they are connected to the ground terminals 5a1 and 5a2, the power terminals 5b1 and 5b2, the vertical ground lines 6b1 and 6b2, power terminals 5b1 and 5b2, and vertical power lines 7b1 and 7b2 through via holes.
Since the power bus 11a and the horizontal ground bus 11b on the semiconductor substrate are arranged on the semiconductor chip with a different design from the macro, no bus is provide at the upper portion of the macro cell in some cases. In this case, the power and ground buses cannot be connected to the ground terminals 5a1, and 5a2, and the power terminals 5b1 and 5b2 through contact holes. For this reason, power and ground buses are formed in a sixth layer in a vertical direction and connected to the ground terminals 5a1, and 5a2, and the power terminals 5b1 and 5b2.
Thus, in the conventional structure, the six-layer wiring is required to supply a current to the macro cell stably.
In connection with power wiring, other macro cells have substantially the same structure as the aforementioned structure.
There has been a growth in the case that the system LSI, which is structured by mounting a plurality of macro cells thereon, is also provided to the portable electronic device, such as a computer of notebook-size, palm-size, pocket-size, etc., personal digital assistants (PDA), or cellular phone, personal handy-phone system (PHS). In such a portable electronic device, since the space is limited, the need for miniaturizing a chip area and the need for improving cost reduction arise.
In conventional, the line widths of the orbital power rings 6 and 7 are narrowed to reduce the chip area. However, the current supplied from the power flows through the orbital power rings 6 and 7 with a narrow line width to bypass the macro cell as shown by arrows, so that a resistance value increases and a current supply capability decreases. Particularly, there is a problem in that a large voltage drop occurs at a connection between the horizontal power wiring 7a1 and the vertical power bus 9b (point A of FIG. 18).
Moreover, a reduction in the cost of semiconductor integrated circuit can be generally achieved by decreasing the number of wiring layers of the semiconductor integrated circuit and the number of processes. However, the general semiconductor integrated circuit needs at least five wiring layers. Particularly, in order to supply a stable current to the macro cell without depending on the presence or absence of the power bus and the ground bus on the semiconductor substrate, the sixth wiring layer is required as mentioned above. Accordingly, there is a problem in that the cost of the semiconductor integrated circuit cannot be reduced.
An object of the present invention is to provide a semiconductor integrated circuit, which can reduce a chip area and has a small number of wiring layers, and its designing method.
A semiconductor integrated circuit according to the present invention includes: a macro cell arranged on a chip; a plurality of power terminals formed on an upper portion of the macro cell, and a plurality of ground terminals formed thereon; a first wiring group including at least one power wiring and one ground wiring extended in a first direction along a first side of the macro cell; a second wiring group including at least one power wiring and one ground wiring extended in the first direction along a second side of the macro cell opposite to the first side; and a third wiring group, which is arranged in a second direction on the macro cell, and which include at least one power wiring and one ground wiring for establishing connection between the first wiring group and the second wiring group, wherein the power wring and the ground wring which form the third wiring group are respectively connected to the corresponding power terminal and the corresponding ground terminal on the macro cell.
With the above structure, connection between the first wiring group and the second wiring group can be made by numerous power wiring and ground wiring, making it possible to reduce a voltage drop therebetween and to connect the power terminals and ground terminals formed on the macro cells.
A semiconductor integrated circuit manufacturing method according to the present invention includes the steps of: arranging a macro cell having a first side, a second side opposite to the first side, a third side, and a fourth side opposite to the third side on a semiconductor chip, and having at least one power terminal and one ground terminal on its top surface; arranging a first wiring group including at least one power wiring and one ground wiring in a predetermined range from the first side and extended in a first direction; arranging a second wiring group including at least one power wiring and one ground wiring in the predetermined range from the second side and extended in the first direction; arranging a third wiring group including at least one power wiring and one ground wiring in the predetermined range from the third side and extended in the second direction so as to connect the first wring group to the second wiring group; arranging a fourth wiring group including at least one power wiring and one ground wiring in the predetermined range from the fourth side and extended in the second direction so as to connect the first wring group to the second wiring group; and arranging a fifth wiring group including at least one power wiring and one ground wiring between the first wring group and the second wiring group in accordance with the power terminal and the ground terminal.
With the above design method, the design of a macro cell and the design of wiring group for supplying the current to the macro cell can be separately carried out.